Multi-processor type storage control apparatus for performing access control through selector

ABSTRACT

A storage control apparatus is coupled to a central processing unit (CPU) and a storage unit to control input/output of data between the CPU and the storage unit. The storage control apparatus has at least two processors coupled to the CPU and the storage unit, a cashe memory (CM) unit for temporarily storing data of the storage unit, a shared memory (SM) unit for storing information concerning control of the CM unit and the storage unit, and a selector coupled to the at least two processors, the CM unit and the SM unit through access paths to selectively apply access requests from the at least two processors to the CM unit and the SM unit.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a multi-processor system havinga shared memory unit and more particularly to a multi-processor typestorage control apparatus.

[0002] In recent storage systems, a system of the type havingmulti-processor architecture has been employed principally with the aimof obtaining higher performance.

[0003] For example, in a prior art shown in “HITAC H8538-C3 type disccontrol apparatus”, p5, 1985, the apparatus has storage directors eachof which controls data transfer between a central processing unit (CPU)and a storage unit, and a cache memory that temporally stores data ofthe storage units. The two or more storage directors are connected tothe cache memory and each of the storage directors has an access path tothe cache memory. Such an arrangement is called “star connection”. Thereare processors running micro programs that control data transmission andrelated hardware in the storage director. The apparatus also has ashared memory which stores information, such as cache and discmanagement data, with-which the processors work consistently. Thestorage directors and the shared memory are connected in a similarmanner to the cache memory through different access paths.

[0004] On the other hand, in another prior art shown in “HITAC A6591type disc control apparatus”, p4, 1997, the control apparatus has aplurality of processors on the host side, a plurality of processors onthe storage unit side, a cache memory unit and a shared memory unit.Each of the processors is coupled to the shared memory unit through acontrol bus and each of the processors is coupled to the cache memoryunit through a data bus.

[0005] In the above prior arts, the shared memory unit has a dualstructure of shared memory sections with the aim of securing thereliability, so that even when one of the shared memory sections isblocked, normal operation of the system can be ensured. In theconventional system, for the purpose of maintaining the dual state ofthe shared memory unit, a method is employed in which when write accessto the shared memory unit occurs, circuits of both the shared memorysections receive the access and at the same time, update a designatedaddress.

[0006] On the other hand, in the former prior art, such control as aboveis not carried out and when there occurs updating, addresses on both theshared memory sections are updated sequentially in accordance with aprogram operated by the processor.

SUMMARY OF THE INVENTION

[0007] To meet a need for high performance required for the storageapparatus system, the control unit is increased in scale and componentsare increased in speed so that for example, the number of processors maybe increased, the capacity of the cache memory unit may be increased,high-performance processors may be employed, the width of internal busesmay be expanded and the bus transfer capability may be improved.

[0008] In the latter prior art disclosed in “HITAC A6591 type disccontrol apparatus”, however, the transfer capability of the internalpaths has been liable to encounter difficulties in following an increasein scale of the system and improvements in performance.

[0009] Especially, the control path has a small transfer amount pertransfer operation, with the result that most of occupation time is usedfor protocol overhead and the transfer capability of the path cannotfulfil itself.

[0010] Accordingly, in order to obtain high memory access performance,it is conceivable to couple the processor and the memory unit in a starconnecting fashion as in the former prior art system disclosed in the“HITAC H-8538-C3 type disc control apparatus”.

[0011] However, the number of access paths for coupling the sharedmemory unit and the cache memory unit increases in proportion to anincrease in the number of carried processors.

[0012] The number of pins in an existing LSI amounts up to a maximum ofabout 600.

[0013] On the other hand, on assumption that the width of access pathsinclusive of control line is about 20 bits and the number of processorsis 64, input lines of 1280 bits in total are laid to each of the sharedmemory unit and the cache memory unit, giving rise to a shortage of thenumber of pins in the LSI.

[0014] Further, since the size of a package is limited, there is anupper limit of the number of connectors on the package, making itimpossible to lay the input lines of 1280 bits.

[0015] Accordingly, a first object of the present invention is toprovide a storage control apparatus having an internal constructionwhich can avoid a shortage of the number of pins and that of the numberof connectors in an LSI and can secure necessarily sufficientperformance.

[0016] On the other hand, in the shared memory unit having a dualstructure, the sequence of access to dual sections by the individualprocessors must be maintained.

[0017] This problem will be described by way of example.

[0018] Incidentally, as will be well known in the art, access to thecache memory unit is carried out by using management information in theshared memory unit. More particularly, management information for eachsegment of the cache memory unit (information indicative of use/nonuseof each segment and information indicative of locking/unlocking of eachsegment) is stored in the shared memory unit. When the processoraccesses the cache memory unit, it decides from the managementinformation in the shared memory unit whether or not a segment to beaccessed is in use. In case the segment is in nonuse, the processoraccesses that segment of the cache memory unit. Through this, aplurality of processors are prevented from writing/reading to/from thecache memory unit simultaneously.

[0019] Thus, it is now assumed that for example, processors a and bupdate the contents of the shared memory unit substantiallysimultaneously.

[0020] If the contents of a section A of the shared memory unit is firstupdated by the processor a and the contents of a section B of the sharedmemory unit is updated by the processor b, followed by subsequentupdating of the contents of the section A by the processor b andsubsequent updating of the contents of the section B by the processor a,the shared memory unit has the ultimate contents including the contentsof section A which is updated by the processor b and the contents ofsection B which is updated by the processor a, thus indicating thatstates of both the sections do not coincide with each other.

[0021] In the aforementioned “HITAC H-6581-C3 disc type controlapparatus”, a method is proposed as a means for securing the accesssequence, according to which the individual processors are exclusivelyORed programmably and thereafter, the same addresses in both the sharedmemory sections are updated sequentially.

[0022] In the above method, however, the memory unit is once locked andthen updated, raising a problem from the standpoint of performance.

[0023] Accordingly, a second object of the present invention is tomaintain the dual state of the two shared memory sections.

[0024] According to an aspect of the present invention, a storagecontrol apparatus coupled to a central processing unit and a storageunit to control input/output of data between the central processing unitand the storage unit, comprises at least two processors coupled to thecentral processing unit and the storage unit, a cache memory unit fortemporarily storing data of the storage unit, a shared memory unit forstoring information concerning control of the cache memory unit and thestorage unit, and a selector coupled to each of the at least twoprocessors, the cache memory unit and the shared memory unit throughaccess paths to selectively apply access requests from the at least twoprocessors to the cache memory unit and the shared memory unit.

[0025] With this construction, the total number of access paths forcoupling the selector and the shared memory unit or the total number ofaccess paths for coupling the selector and the cache memory unit can besmaller than the total number of access paths for coupling the at leasttwo processors and the selector, thereby reducing the number of paths(pins) laid to each memory unit. A similar effect can also be attainedwhen a single memory unit is used to serve as both a cache memory unitand a shared memory unit.

[0026] According to an embodiment of the present invention, the sharedmemory unit includes paired two shared memory sections each coupled tothe selector, the two shared memory sections are coupled to each otherby an inter-shared memory path, the selector applies an access requestfrom one of the at least two processors to one of the two shared memorysections, the one shared memory section responds to the applied accessrequest to perform an access process and sends a command to the other ofthe two shared memory sections, and the other shared memory sectionresponds to the command to perform an access process. With thisconstruction, by making a read/write access request to one of the twoshared memory sections through the selector, the read/write processesfor the two shared memory sections can be carried out simultaneously.

[0027] According to another embodiment of the present invention, thecache memory unit has a dual structure of first and second cache memorysections, the processors send access requests to the selector, and theselector responds to the access requests to access the two cache memorysections. With this construction, in accordance with the access requestsmade by the processors through one operation, the two cache memorysections can be accessed.

[0028] According to still another embodiment, the cache memory unit hasa dual structure of first and second cache memory sections, theprocessors send to the selector commands for designating data copyingbetween the first and second cache memory sections, and the selectorresponds to the commands to perform the data copying between the firstand second cache memory sections. With this construction, the datacopying between the two cache memory sections can be effected by onecommanding operation from the processors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029]FIG. 1 is a block diagram showing an embodiment of typicalconstruction of a storage control apparatus according to the presentinvention.

[0030]FIG. 2 is a diagram showing a first embodiment of the sequence ofaccess to a shared memory (SM) unit according to the invention.

[0031]FIG. 3 is a circuit diagram showing an embodiment of constructionof a SM selector shown in FIG. 1.

[0032]FIG. 4 is a flow chart showing the operation of a SM accesscircuit in FIG. 1.

[0033]FIG. 5 is a flow chart showing the operation of a controller inthe FIG. 3 SM selector.

[0034]FIG. 6 is a flow chart continuing from FIG. 5.

[0035]FIG. 7 is a block diagram showing an embodiment of construction ofa shared memory unit.

[0036]FIG. 8 is a flow chart showing a first embodiment of the operationof a SM controller.

[0037]FIG. 9 is a diagram showing a second embodiment of the sequence ofSM access.

[0038]FIG. 10 is a flow chart showing a second embodiment of theoperation of the SM controller.

[0039]FIG. 11 is a flow chart continuing from FIG. 10.

[0040]FIG. 12 is a diagram showing an embodiment of write sequence in CMaccess.

[0041]FIG. 13 is a diagram showing another embodiment of write sequencein CM access.

[0042]FIG. 14 is a diagram showing an embodiment of copy sequence in CMaccess.

[0043]FIG. 15 is a diagram showing another embodiment of copy sequencein CM access.

[0044]FIG. 16 is a block diagram showing an embodiment of basicconstruction of the storage control apparatus according to theinvention.

[0045]FIG. 17 is a block diagram showing a modification of the FIG. 16storage control apparatus.

[0046]FIG. 18 is a block diagram showing another embodiment of basicconstruction of the storage control apparatus according to theinvention.

[0047]FIG. 19 is a block diagram showing a modification of the storagecontrol apparatus shown in FIG. 18.

[0048]FIG. 20 is a block diagram showing a modification of the storagecontrol apparatus shown in FIG. 16.

[0049]FIG. 21 is a block diagram showing a modification of the storagecontrol apparatus shown in FIG. 20.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] Embodiments of a storage control apparatus according to thepresent invention will now be described with reference to theaccompanying drawings.

[0051] Referring to FIG. 1, there is illustrated an embodiment oftypical construction of the storage control apparatus according to theinvention.

[0052] The storage control apparatus, as designated by reference numeral195, has at least two microprocessor (MP) units 110A and 110B, a sharedmemory (SM) selector 140, a cache memory (CM) selector 150, a SM unit160, and a CM unit 170.

[0053] In this example, the MP unit 110A has a dual structure of MPsections 110Aa and 110Ab and the MP unit 110B also has a dual structureof MP sections 110Ba and 110Bb. Similarly, the SM selector 140 has adual structure of SM selector sections 140 a and 140 b and the CMselector 150 also has a dual structure of CM selector sections 150 a and150 b. Further, the SM unit 160 has a dual structure of SM sections 160a and 160 b and the CM unit 170 also has a dual structure of CM sections170 a and 170 b.

[0054] Each of the MP sections 110Aa and 110Ab is coupled to a centralprocessing unit (CPU) 225 or a storage unit 226 and in this example, tothe CPU 225 by a path 180A which is, for example, a SCSI path. On theother hand, each of the MP sections 110Ba and 110Bb is coupled to theCPU 225 or the storage unit 226 and in this example, to the storage unit226 by a path 180B which is also, for example, a SCSI path.

[0055] Each of the MP sections 110Aa and 110Ab is coupled to therespective SM selector sections 140 a and 140 b through access paths120A and is also coupled to the respective CM selector sections 150 aand 150 b through access paths 130A. Similarly, each of the MP sections110Ba and 110Bb is coupled to the respective SM selector sections 140 aand 140 b through access paths 120B and is also coupled to therespective CM selector sections 150 a and 150 b through access paths130B.

[0056] Each of the SM selector sections 140 a and 140 b is coupled tothe respective SM sections 160 a and 160 b through access paths 125.Similarly, each of the CM selector sections 150 a and 150 b is coupledto the respective CM sections 170 a and 170 b through access paths 135.

[0057] Each of the MP sections 110Aa, 110Ab, 110Ba and 110Bb includesone or more processors (MP's) 111, a CM access circuit 112 and a SMaccess circuit 113.

[0058] The MP 111, CM access circuit 112 and SM access circuit 113 ineach of the MP sections 110Aa, 110Ab, 110Ba and 110Bb function as willbe described below.

[0059] The MP 111 in each of the MP sections 110Aa and 110Ab executesdata transfer between the CPU 225 and each of the SM sections 160 a and160 b by way of each of the SM selector sections 140 a and 140 b andalso executes data transfer between the CPU 225 and each of the CMsections 170 a and 170 b by way of each of the CM selector sections 150a and 150 b.

[0060] Similarly, the MP 111 in each of the MP sections 110Ba and 110Bbexecutes data transfer between the storage unit 226 and each of the SMsections 160 a and 160 b by way of each of the SM selector sections 140a and 140 b and also executes data transfer between the storage unit 226and each of the CM sections 170 a and 170 b by way of each of the CMselector sections 150 a and 150 b.

[0061] The CM access circuit 112 in each of the MP sections 110Aa and110Ab is a dynamic memory access (DMA) circuit which is coupled to thepaths 130A to execute, in response to a request from the MP 111, datatransfer between each of the CM sections 170 a and 170 b and the CPU 225by way of the paths 130A, the paths 135 and each of the CM selectorsections 150 a and 150 b. Similarly, the CM access circuit 112 in eachof the MP sections 110Ba and 110Bb is a DMA circuit which is coupled tothe paths 130B to execute, in response to a request from the MP 111,data transfer between each of the CM sections 170 a and 170 b and thestorage unit 226 by way of the paths 130B, the paths 135 and each of theCM selector sections 150 a and 150 b.

[0062] A buffer 115 in each MP section 110Aa or 110Ab is coupled to theCPU 225 through the path 180A and is used to temporarily store data inresponse to a command from the CM access circuit 112. Similarly, abuffer 115 in each MP section 110Ba or 110Bb is coupled to the storageunit 226 through the path 180B and is used to temporarily store data inresponse to a command from the CM access circuit 112.

[0063] A local memory (LM) 114 connected to the CM access circuit 112 isused as a memory which is used for work by the processor or for storageof read data and write data.

[0064] The SM access circuit 113 in each of the MP sections 110Aa and110Ab is coupled to the paths 120A and responds to a request from the MP111 to execute data transfer from each of the SM sections 160 a and 160b to the MP 111 or data transfer from the MP 111 to each of the SMsections 160 a and 160 b through the paths 120A, each of the SM selectorsections 140 a and 140 b and the path 125. Similarly, the SM accesscircuit 113 in each of the MP sections 110Ba and 110Bb is coupled to thepaths 120B and responds to a request from the MP 111 to execute datatransfer from each of the SM sections 160 a and 160 b to the MP 111 ordata transfer from the MP 111 to each of the SM sections 160 a and 160 bthrough the paths 120B, each of the SM selector sections 140 a and 140 band the path 125.

[0065] Each of the SM selector sections 140 a and 140 b functions toselect one of requests for access to the SM sections 160 a and 160 b,which are delivered from the respective MP sections 110Aa, 110Ab, 110Baand 110Bb through the paths 120A and paths 120B, so as to execute accessto either the corresponding SM section 160 a or 160 b in response to theselected access request.

[0066] Each of the CM selector sections 150 a and 150 b functions toselect one of requests for access to the CM sections 170 a and 170 b,which are delivered from the respective MP units 110Aa, 110Ab, 110Ba and110Bb through the paths 130A and 130B, so as to execute access to eitherthe corresponding CM section 170 a or 170 b in response to the selectedaccess request.

[0067] In the present embodiment, the SM selector is constructedseparately from the CM selector but obviously, apart from the separateconstruction, a single selector may be so constructed as to serve bothas a SM selector and a CM selector.

[0068] The SM unit 160 is adapted to store control information such ascache management information and system management information andincludes the two SM sections 160 a and 160 b which are paired.

[0069] Data stored in the SM unit 160 is dual for the paired SM sectionsso that the same data may be stored at addresses which are the same forthe paired SM sections.

[0070] Accordingly, even in the event that one of the SM sections 160 aand 160 b is blocked up, no system down results.

[0071] The duality of the stored data can be realized by coupling the SMsections 160 a and 160 b through an inter-SM path 165.

[0072] In the present embodiment, the SM unit 160 and CM unit 170 aredescribed as being memory modules which are independent from each otherbut structurally, it is conceivable that part of the CM unit 170 is usedas a SM unit 160 (see FIG. 18).

[0073] On the other hand, the CM unit 170 is a memory unit adapted totemporarily store data which prevails on the storage unit. Write datafrom the CPU (host) which has already been written in the CM unit 170but has not been written in the storage unit yet (that is, dirty data)is stored in the dual form in the two CM sections 170 a and 170 b.

[0074] The duality in the CM unit 170 differs from that in the SM unit160 in that the same data is not always stored at cache addresses whichare the same for the CM sections 170 a and 170 b.

[0075] Management information of the CM unit 170 is stored in the SMunit 160 and the duality of the CM unit 170 can be realized by causingthe MP 111 to first access the SM unit 160 so as to secure data storageareas on the CM sections 170 a and 170 b and to write write data inthese areas.

[0076] Accordingly, such a mechanism as the inter-SM access path 165 isunneeded between the CM sections 170 a and 170 b.

[0077] Each of the MP sections 110Aa, 110Ab, 110Ba and 110Bb is coupledto the two different SM selector sections 140 a and 140 b by the two SMaccess paths 120A or 120B and is also coupled to the two different CMselector sections 150 a and 150 b by the two CM access paths 130A or130B.

[0078] Thus, each of the SM selector sections 140 a and 140 b is coupledwith the four MP sections 110Aa, 110Ab, 110Ba and 110Bb and similarlyeach of the CM selector sections 150 a and 150 b is coupled with thefour MP sections 110Aa, 110Ab, 110Ba and 110Bb.

[0079] Each of the SM selector sections 140 a and 140 b is coupled toeach of the SM sections 160 a and 160 b by the single SM access path 125and similarly, each of the CM selector sections 150 a and 150 b iscoupled to each of the CM sections 170 a and 170 b by the single CMaccess path 135.

[0080] In this manner, the four MP sections 110Aa, 110Ab, 110Ba and110Bb, two SM selector sections 140 a and 140 b and two CM selectorsections 150 a and 150 b form one group which will be called hereinaftera selector group 190.

[0081] The control apparatus has one or more selector groups 190. In theexample of FIG. 1, only one selector group is illustrated.

[0082] The number of MP units, SM selectors, CM selectors, CM units andSM units has been exemplified hereinbefore for mere explanation and itis not limitative.

[0083] Importantly, the number of the MP units 110 is made to be smallerthan that of the SM selectors 140 in the selector group 190, therebyensuring that the number of the SM access path 125 for coupling the SMselector 140 and the SM unit 160 can be smaller than that of the SMaccess paths 120 for coupling the MP unit 110 and the SM selector 140and a shortage of the number of pins of a LSI carried on the SM unit 160and a shortage of the number of connectors of a package of the SM unit160 can be eliminated.

[0084] This holds true for the CM unit 170.

[0085] For example, when two independent SM access paths 120 (of whichone is for alternate path) extending from 32 MP sections are coupleddirectly to each of the SM sections 160 a and 160 b, the total number ofthe SM access paths 120 coupled to the SM sections 160 a and 160 bamounts up to 32 (MP sections)×2(paths)=64.

[0086] On the assumption that each of the SM access paths 120 has awidth of 16 bits, the SM unit 160 requires pins of 1024 bits but atpresent, a LSI having the number of pins as above is not available.

[0087] On the other hand, according to the present embodiment, 8selector groups 190 are provided for 32 MP sections and the number ofthe SM access paths 120 coupling to each of the SM sections 160 a and160 b is reduced to 8 (selector groups)×2 (SM selector sections)=16,with the result that the number of pins amounting up to 256 suffices.

[0088] Next, a first embodiment of access to the SM unit will bedescribed.

[0089] Referring to FIGS. 1 to 6, the procedure for SM access will firstbe described. In the following description, as an example will bedescribed in which the MP section 110Aa accesses the SM unit 160 throughthe SM selector section 140 a.

[0090] An example of the sequence of access to the SM unit 160 in thepresent embodiment is shown in FIG. 2.

[0091] The MP 111 transfers to the SM access circuit 113 an address ofSM unit 160 (SM sections 160 a and/or 160 b) to be accessed, an addressof LM 114 at which data is expected to be stored in case of readoperation and an address of LM 114 at which write data has been storedin case of write operation.

[0092] When receiving a request for read access to the SM unit from theMP 111, the SM access circuit 113 transmits a REQ signal to the SMselector section 140 a and waits until an ACK signal is returned fromthe SM selector section 140 a. After receiving the ACK signal, the MP111 transmits a read command and a read address.

[0093] The SM selector section 140 a selects one of SM read accessrequests delivered out of the plurality of MP sections and returns theACK signal to an originator MP section (here, MP section 110Aa) whichhas transmitted the selected access request.

[0094] When subsequently receiving the command and address from the MPsection 110Aa, the SM access circuit 113 transmits the command andaccess to the SM sections 160 a and 160 b in case of dual access.

[0095] When the SM unit 160 receives the command and address, it readsdata from that address, transfers the read data to the SM selectorsection 140 a and then transmits an end report to the SM selectorsection 140 a.

[0096] When receiving the initial read data and the end report from theSM section 160 a or 160 b, the SM selector section 140 a transmits thatdata and the end report to the MP section 110Aa.

[0097] At that time, the read data is temporarily stored in a buffer ofthe SM selector section 140 a.

[0098] When the SM selector section 140 a subsequently receives anotherread data from the SM section 160 a or 160 b, it compares the newlyreceived read data with the read data which has been stored in thebuffer to confirm coincidence.

[0099] Thereafter, the SM selector section transfers a received endreport to the MP section 110Aa, thereby completing the process. When theSM access circuit 113 receives the read data, it stores that data at theaddress of LM 114 which has been designated by the MP 111.

[0100] Thereafter, the MP section 110Aa receives the aforementioned twoend reports, thereby completing the process.

[0101] In case of the write process, the procedure proceeds similarly,so that the SM access circuit 113 transmits write data following acommand and an address.

[0102] The SM selector 140 transfers the command, address and write datato the SM sections 160 a and 160 b, which store the write data at thedesignated address and then makes an end report.

[0103] Referring now to FIG. 3, there is illustrated an example ofinternal construction of each of the SM selector sections 140 a and 140b.

[0104] Registers 310 are provided in association with the respective SMaccess paths 120A and 120B through which each of the MP sections 110Aa,110Ab, 110Ba and 110Bb is coupled to each of the SM selector sections140 a and 140 b, and a controller 300 can transmit/receive informationto/from the respective MP sections by reading/writing the respectiveregisters 310. Since the 8 SM access paths 120 are provided inassociation with the 4 MP sections in FIG. 1, there are provided 8registers 310 corresponding to the individual SM access paths in FIG. 3.

[0105] On the other hand, registers 340 a and 340 b are provided incorrespondence to the respective SM access paths 125 through which therespective SM sections units 160 a and 160 b are coupled to the SMselector 140 and communication with the SM unit 160 can be ensured byreading/writing the registers 340 a and 340 b.

[0106] Data read out of the SM section 160 a or 160 b can be transferredto the MP section which has made the access request through thecorresponding register 310 and at the same time can be stored incorresponding one of buffers 330 a and 330 b.

[0107] Then, after data are read out of the two SM sections 160 a and160 b, coincidence of the data, that is, duality is checked by means ofa data comparator 320.

[0108] The controller 300 functions to select and execute one of accessrequests delivered out of the respective MP sections 110Aa, 110Ab, 110Baand 110Bb and to control the data comparator 320.

[0109] Referring to FIG. 4, there is illustrated a flow chart of theprocess in the SM access circuit 113 of each MP section.

[0110] When the SM access circuit 113 receives a SM access request froma MP 111, it is checked in step 400 whether, for example, the eighth bitof an address of the SM unit 160 is “0” and if “0”, the SM selectorsection 140 a is selected in step 410 and the request signal istransmitted to the SM selector section 140 a.

[0111] If the eighth bit is “1”, the SM selector section 140 b isselected in step 420 and the request signal is transmitted to the SMselector section 140 b.

[0112] Since each MP section has the SM access paths 120 (120A, 120B;paths “0”, “1”) directed to the respective two SM selector sections 140a and 140 b, it is efficient that the two paths are distributed inaccordance with loads. Accordingly, in the present embodiment, theaddress on the SM access path is switched from an address for the SMselector section 140 a to that for the SM selector section 140 b or viceversa, for example, every 128 bytes.

[0113] Therefore, by consulting the 8

th bit of the access address, it can be determined which SM selectorsection is to be selected.

[0114] Generally, the access path is selected by consulting the n-th bitand switching between the SM selector sections 140 a and 140 b iscarried out every 2^((n−1)) bytes.

[0115] The value of n may be settled by examining the SM access patternin the system.

[0116] Thus, in the event that one of the selector sections 140 a and140 b becomes faulty, the faulty selector is made to be unusable. Inthis case, the step 400 is skipped to permit the request signal to betransmitted to a normal selector section.

[0117] When an ACK signal is returned from the selected SM selectorsection 140 a or 140 b in response to the transmitted REQ signal in step411 or 421, a command and an access address are transmitted to theselected SM selector section 140 a or 140 b in steps 412 and 413 orsteps 422 and 423.

[0118] In case the access is for reading, data is subsequently receivedthrough the selected SM selector in step 414 or 424 and the data isstored at an address of LM 114 designated by the MP.

[0119] In case the access is for writing, following the steps 413 and414 or the steps 423 and 424, write data is transmitted from an addressof LM 114 designated by the MP 111 to the SM unit 160 through theselected SM selector section.

[0120] Finally, when the SM access circuit 113 receives an end reportfrom the SM section 160 a and that from the SM section 160 b through theselected SM selector section 140 a or 140 b in step 415, the process iscompleted.

[0121] The reasons why the interchange of REQ and ACK signals is neededin the steps 410 and 411 or steps 420 and 421 will now be described.

[0122] The SM selector 140 sequentially executes access requests fromthe plurality of MP's as will be detailed later and therefore, it isforced to wait when the access requests interfere.

[0123] Accordingly, the SM access circuit 113 first transmits a requestsignal and then starts processing when an ACK signal responsive to therequest signal is returned from the SM selector.

[0124] Command data transmitted from the SM access circuit 113 to the SMselector 140 includes information indicative of either read or write, aflag indicative of either dual access or single access and informationindicating which one of the SM sections 160 a and 160 b is to beaccessed in case of single access.

[0125] Referring now to FIGS. 5 and 6, the processing in the controller300 of each SM selector sections 140 a or 140 b will be described.

[0126] In steps 510 and 511, the controller 300 supervises the registers310(#0) to 310(#7) to check them for on-state of their REQ flags in around robin fashion.

[0127] When a register 310 being in the flag on-state is found, an ACKsignal is returned to the corresponding path to inform the register 310that the process is ready to start. This can be accomplished by turningon a bit corresponding to ACK of that register 310.

[0128] Subsequently, in step 512, the command and address received fromthe SM access circuit 113 are transferred to both the SM section A (160a) and the SM section B (160 b).

[0129] The command is then decoded. If the command is determined to be aread command in dual access, the controller 300 waits for read dataexpected to be transferred from the SM unit 160 in step 514.

[0130] In case of dual access, it is necessary to confirm that data readout of the SM section A 160 a coincides with data read out of the SMsection B 160 b.

[0131] Since the access process to the SM section A is carried outindependently of the access process to the SM section B, the sequence ofdata read operation is not fixed.

[0132] Accordingly, when the read data from one section is received instep 514, it is checked in step 515 whether data from the other sectionhas been received.

[0133] If the reception has been completed, the received data is storedin the buffer 330 in step 516. The initially received data istransferred to the MP.

[0134] If the data now received is from the SM section A 160 a, it isstored in the buffer 330 a but if from the SM section B, it is stored inthe buffer 330 b. Thereafter, the controller 300 commands the datacomparator 320 to compare the data.

[0135] If the comparison result is determined not to be abnormal in step518 and the SM unit 160 makes a report on a normal end in step 517, theaccess is determined to be successful and the normal end is reported tothe SM access circuit 113 in step 519, thus completing the process.

[0136] When read data is not received from the other section in the step515, indicating that data now received is initially transferred from theSM unit 160, the received data is stored in the buffer 330 a for sectionA in step 520 when it is from the SM section A 160 a but in the buffer330 b for section B when it is from the SM section B 160 b.

[0137] In addition to the storage in the buffer 330, the read data istransferred to the SM access circuit 113.

[0138] Thereafter, in steps 521 and 522, an end report received from theSM unit 160 is transferred to the SM access circuit 113.

[0139] By storing the data in the buffer 330 in this manner, the datacan be held for subsequent comparison.

[0140] At the time that the initial read data is received from the SMunit 160, that data is transferred to the SM access circuit but dataread subsequently is not transferred. This is because by reducing thenumber of data transfer operations to one, wasteful transfer overheadcan be reduced.

[0141] In case any report on normal end is not received from the SM unitin the step 517 or 521, an abnormal end is reported to the MP in step523.

[0142] When the request from the SM access circuit 113 is determined tobe for either write access or single read access in the step 513, theprocessing shown in FIG. 6 is carried out.

[0143] In case of write access request, write data received from the SMaccess circuit 113 is transferred to the SM section A 160 a and SMsection B 160 b in step 620 and when completion reports are receivedfrom the two sections in step 621, they are transferred to the SM accesscircuit 113.

[0144] In case of single read request, read data received from adesignated section in step 611 is transferred to the SM access circuit113 and thereafter, when a completion report is received from thedesignated section in step 612, it is transferred to the SM accesscircuit 113, thus completing the process.

[0145] In case of either single read access or write access, the commandand address are transferred to both the SM section A 160 a and the SMsection B 160 b. But when decoding the command, the SM unit 160 decideswhether the access is directed to the SM unit 160 of its own and if theprocessing is unneeded, it neglects the request.

[0146] By doing so, the SM selector need not decide whether the accessis for single access and can be reduced in load.

[0147] In connection with access to the SM unit 160, there are two kindsof access modes of which one is dual access for accessing the paired twosections of the SM unit 160 and the other is single access for accessingone of the two sections.

[0148] This is because control information includes information storedin a single fashion and information stored in a dual fashion. Forexample, the former information is cache management information and thelatter is system management information.

[0149] In case of dual access, the SM unit 160 must observe the sequenceof access.

[0150] The reasons for this will be first described by way of example.

[0151] It is now assumed that a processor No. 1 is about to update thecontents of the SM unit 160 to A and at the same time, a processor No. 2is about to update the contents at the same address to B.

[0152] If the processors Nos. 1 and 2 execute access to the SM section A160 a in this order and the processors Nos. 2 and 1 execute access tothe SM section B 160 a in this order, the ultimate contents at thecorresponding address is updated to B on the SM section A 160 a and to Aon the SM section B 160 b, so that non-coincidence of data is caused.

[0153] This will be explained by making reference to another example.

[0154] It is now assumed that the contents of the SM unit 160 is A andthe processor No. 1 is about to read the contents of the SM unit 160 andat the same time, the processor No. 2 is about to update the contents atthe same address to B.

[0155] If the processors Nos. 1 and 2 execute access to the SM section A160 a in this order and the processors Nos. 2 and 1 execute access tothe SM section B 160 b in this order, data before updating, that is, Ais read out of the SM section A and data after updating, that is, B isread out of the SM section B, so that non-coincidence of data isdetected.

[0156] As will be seen from the above example, control for maintainingthe dual state of the SM unit 160 is necessary.

[0157] According to a basis idea for controlling the maintenance of thedual state, one of the SM sections 160 a and 160 b is defined as masterwith the other defined as slave and the slave is not allowed to beaccessed until the master permits execution of the access.

[0158] Conceivably, switching between the master and the slave can beeffected by various methods including a method in which the unit ofsection, for example, SM section 160 a is always defined as master andthe SM section 160 b is always handled as slave and another method inwhich the switching is carried out address area by address area, forexample, the SM section 160 a and SM section 160 b are switched frommaster to slave or vice versa every 256 bytes.

[0159] The present embodiment presupposes the latter method in whichswitching between master and slave is carried out every address unit.

[0160] In this case, a register holding an address unit, for example, isprovided in each of the SM unit 160 and SM selector 140 and uponstart-up of the system, the MP sets the register. When a SM access isgenerated, each of the SM unit 160 and selector 140 compares the accessaddress with the address unit stored in the register to examine whichone of the two sections is determined to serve as a master.

[0161] Referring to FIG. 7, the SM unit 160 is constructed as showntherein.

[0162] The SM unit 160 comprises MP interfaces (MP IF) 170 each adaptedto perform transmission/reception of information between the SM selector140 and the SM unit, a SM transmission interface 720 for transmittinginformation to the other section of duality, a SM reception interface730 for receiving information from the other section, memory banks 750each adapted to store data, memory controllers 740 each adapted tocontrol read/write from/to the memory bank, and a SM controller 700 forcontrolling the MP interfaces 710, SM transmission interface 720, SMreception interface 730 and memory controllers 740.

[0163] The processing in the SM controller 700 is shown in a flow chartof FIG. 8.

[0164] Firstly, in step 800, an address of an object to be accessed isacquired from the SM reception interface 730.

[0165] If the acquired address is null, the MP interfaces 710 aresequentially examined in step 810 to find whether there is an accessrequest from the MP 111.

[0166] In the presence of the access request, the MP interface 710 holdsa command and an address as well as write data in case of writeoperation.

[0167] Then, the address is first acquired and it is examined whetherthe address is one to be processed by the section of its own whichserves as master.

[0168] In the absence of an access request for which the section of itsown serves as master, the program returns to the step 800 to continuepolling.

[0169] In the presence of the access request for which the section ofits own serves as master, it is examined in accordance with the commandin step 811 whether the access request is for dual access.

[0170] If the access request is for dual access, that address istransmitted to the SM transmission interface 720 in step 812, therebyrequesting the slave section to process that request.

[0171] Subsequently, in step 813, a corresponding address is accessed.

[0172] In the presence of a read request, the read request and anaddress are transmitted to the memory controller 740.

[0173] When the memory controller 740 accesses the memory bank 750 anddata is read, the SM controller 700 transfers that data to the MPinterface 710, thereby completing the process.

[0174] In case of write access, a write request is transmitted to thememory controller 740 with an address and write data transferredthereto.

[0175] The memory controller 740 writes the data at the designatedaddress to thereby complete the process.

[0176] When the above processing is completed normally, the SMcontroller 700 reports a normal end to the MP 111 through the MPinterface 710 and the program returns to the step 800.

[0177] Next when the address stored in the SM reception interface 730 isdetermined to be non-null in the step 800, indicating that a processrequest from the master section is present, the MP interfaces 710 arescanned in step 820 to decide whether there is an access request whichcoincides with a designated address.

[0178] In the presence of the coincident address, access to that addressis executed in step 813.

[0179] In the absence of the coincident address, the MP interfaces 710are sequentially supervised in the step 830 until the same accessrequest occurs.

[0180] If no access request occurs at the termination of a predeterminedwaiting time, a time-out error is reported to the MP 111.

[0181] It is slightly inefficient to sequentially search the MPinterfaces 710 to find an access request having an address whichcoincides with that received from the SM reception interface 730.

[0182] Therefore, conveniently, when a request is issued from the mastersection, it is decided which one of the MP interfaces 710 the requestcorresponds to.

[0183] To this end, for example, a MP number assigned definitely in thesystem is stored in the command and the MP number is transmitted to theSM transmission interface 720.

[0184] Further, two MP interfaces 710 to which the respective SMselector sections are connected are settled fixedly and the selectorsection has a correspondence table indicating a MP number and acorresponding MP interface.

[0185] With this construction, the number indicative of the MP interface710 can be settled definitely in the slave from the MP number receivedfrom the SM reception interface 730 and the program can immediatelyshift from the step 820 to the step 813.

[0186] According to the above method, the control operation is carriedout through the SM transmission interface 720 and SM reception interface730 and in the dual access, the slave section is not permitted toperform the address process before the master section starts theprocess, so that the access sequence can always be observed to therebyprevent the aforementioned non-coincidence of data from occurring.

[0187] Next, a second embodiment of the SM access will be described. Inthe second embodiment, the second securing method is employed to securethe sequence of access to the SM unit 160 in the dual access.

[0188] Reference is now made to FIGS. 9 to 11 to describe the secondembodiment.

[0189] An example of SM access protocol in read access is shown in FIG.9.

[0190] In the second securing method according to the second embodiment,the SM selector 140 transmits an access request to only a SM sectionwhich serves as master.

[0191] Here, it is assumed that the SM section 160 a is the master andthe SM section 160 b is a slave.

[0192] In case of read access, when receiving an access request, the SMsection 160 a transmits a command and an address to the SM section 160 bthrough the inter-SM access path 165 and besides accesses the memory soas to read data.

[0193] The SM section 160 b reads the data from the memory in responseto the access request, transmits the data to the SM section 160 a andthereafter makes an end report to the SM section 160 a.

[0194] When receiving the data and the end report from the SM section160 b, the SM section 160 a confirms that the data is read normally andthen compares data read out of the memory of its own with the datareceived from the SM section 160 b. If the data coincide with eachother, the SM section 160 a transmits the received data to the SMselector 140 and makes an end report.

[0195] In case of write access, when receiving write data from the SMselector 140 following reception of a command and an address, the SMsection 160 a transmits the command, address and data to the SM section160 b and stores the data in the memory at a designated address.

[0196] On the other hand, the SM section 160 b stores the data at anaddress designated by the SM section 160 a and thereafter makes an endreport to the SM section 160 a.

[0197] When the write operation to the memory of its own ends and theend report from the SM section 160 b is received, the SM section 160 amakes an end report to the SM selector 140.

[0198] When receiving an access request from the MP section, the SMselector 140 transfers the access request to only the SM section whichserves as master.

[0199] The waiting process required for the data comparison and dualaccess is handled by the SM unit 160.

[0200] Referring to FIG. 10, the processing carried out in the SMcontroller 700 is shown.

[0201] In step 1000, the SM controller 700 accesses the SM receptioninterface 730 to examine the presence or absence of an access requestfrom the master section.

[0202] If the access request is present, a command and an address aswell as write data in case of write operation are stored in the SMreception interface 730.

[0203] In the absence of the access request, the SM controller 700sequentially accesses the MP interfaces 710 in step 1010 to acquire anaddress and decides whether there is an access request for which thesection of its own serves as master.

[0204] In the absence of the access request, the program returns to thestep 1000, so that polling is repeated.

[0205] If the access request for which the section of its own serves asmaster is present, the command is decoded in step 1011 to examinewhether the access request is for dual access. If the access request isfor double access, the access request including a command and an addressas well as write data in case of write operation is transferred to theSM transmission interface 720 in step 1012.

[0206] Additionally, in case there is a read access request, data isread out of the memory of its own in step 1014 and thereafter, the SMcontroller waits for data transfer and an end report from the slave.

[0207] Receiving the end report, the controller 700 compares in step1015 data read out of the memory of its own with the read datatransferred from the slave and if coincident, the controller 700transfers that read data through the MP interface 710 and SM selector140 and then makes an end report.

[0208] In case the comparison result indicates non-coincidence of data,data read operation from the master section fails or an abnormal end isreported from the slave section, the controller 700 makes an abnormalreport to the MP 111.

[0209] When a write access request is determined in the step 1013, writedata is stored in the memory of its own at a designated address and thenthe controller 700 waits for an end report from the slave in step 1030.

[0210] Subsequently, when the access to the memory of its own endsnormally and a report on normal end is made from the slave in step 1031,the controller 700 makes an end report to the MP 111 through the MPinterface 710 and SM selector 140.

[0211] In case the access to the memory of its own ends abnormally or areport on abnormal end is made from the slave, the controller 700reports an abnormal end to the MP 111 and completes the process.

[0212] When a single access request is determined in the step 1011, thecontrol for dual access set forth so far is unneeded.

[0213] Accordingly, the controller 700 executes access to the memory ofits own and makes an end report to the MP 111, thereby completing theprocess.

[0214] When the presence of an access request from the master section isdetermined in the step 1000 and the access request is for read access,the controller 700 reads data from the memory of its own in step 1110 ofFIG. 11, transfers the data to the master and makes an end report.

[0215] If the access request is for write access, the controller 700stores data in the memory of its own in step 1120 and makes an endreport to the master, thereby completing the process.

[0216] According to the second embodiment of the securing method, theslave executes the process after receiving the access request from themaster.

[0217] Therefore, the sequence of access can be warranted without fail.

[0218] In the first embodiment, the SM selector 140 causes thecompletion of access to the master to meet the completion of access tothe slave and each of the SM sections 160 a and 160 b can release thememory when the access to the memory of its own is completed.

[0219] On the other hand, in the second embodiment, the master waits forthe completion of access to the slave and hence occupation of the SMunit 160 is prolonged by a waiting time.

[0220] Therefore, from the standpoint of performance, the firstembodiment is preferable.

[0221] Next, a method of accessing the CM unit 170 according to theinvention will be described.

[0222] The CM unit 170 is a memory unit for temporarily storing dataexpected to be stored in the storage unit and especially, dirty data isstored in the CM unit 170 in a dual fashion. The dirty data is writedate from the host which is stored in the SM unit 170 but is notreflected on the storage unit.

[0223] Being different from duality in the SM unit 160, the dual data isstored at areas in CM sections 170 a and 170 b which are secured by aprogram operated by the MP 111 and hence the dual data is stored atdifferent areas.

[0224] The comparing check as effected in the read access to the SM unit160 is not executed.

[0225] The construction of the CM selector 150 is substantially the sameas that of SM selector 140 shown in FIG. 3 with the only exception thatthe data comparator 320 and the buffers 330 are not provided becausecomparison of cache data is not carried out as described above.

[0226] Also, the construction of the CM unit 170 is substantially thesame as that of SM unit 160 shown in FIG. 7 with the only exception thatcomponents corresponding to the SM transmission interface 720 and SMreception interface 730 are not provided because the same data is notstored at the same address in a dual fashion and the access sequenceneed not to be warranted.

[0227] An embodiment of a method of storing write data in the CM unit170 will be described.

[0228] It is now assumed that the MP 111 has already acquired a CM areaat which the write data is expected to be stored.

[0229] The MP 111 sets in the CM access circuit 112 a CM address a and aCM address b at which a command and data are to be stored and starts theCM access circuit 112.

[0230] Here, the CM address a and the CM address b are addresses on theCM sections 170 a and 170 b, respectively.

[0231] With the CM access circuit 112 started, the data is divided intopackets having each a constant size and being transferred sequentially.

[0232] Each packet is assigned with a command and an address which areupdated by the CM access circuit 112 as the execution of data transferproceeds.

[0233] For example, when data of 24 KB is transferred from an address ain the form of packets each being of 2 KB, an initial packet is assignedwith a write command and the address a, the next packet is assigned witha write command and an address (a+2048), and an n-th packet is assignedwith a write command and an address (a+2048×(n−1) so that the whole datamay be transferred to the CM unit 170 in the form of 12 packets intotal.

[0234] Referring now to FIG. 12, dual write to the CM unit will bedescribed.

[0235] In the present embodiment, data is first written to one section(in the example of FIG. 12, CM section 170 a) and then written to theother section (in the example of FIG. 12, CM section 170 b).

[0236] Accordingly, the MP 111 first prepares a DMA list for CM section170 a, that is, a list consisting of a command, an address and atransfer length and describing the contents of the process in the CMaccess circuit 112 and a DMA list for CM section 170 b and thereafterstarts the CM access circuit.

[0237] In respect of each address to be transferred, the CM accesscircuit 112 selects which one of the MP-CM access paths is used.

[0238] The selection is carried out through a method similar to thatexplained in connection with the SM access circuit 113, so that theMP-CM access path 130 to be used can be switched, for example, every 32KB.

[0239] When the MP-CM access path is selected, a REQ signal and acommand of an initial packet are transmitted to the CM selector 150.

[0240] The command includes the read/write type, a flag indicatingwhether the access is for dual access, a flag indicating transfer to thesection a and a flag indicating transfer to the section b.

[0241] When the CM selector 150 knows from the command that write to theCM section 170 a prevails, it transmits the REQ signal and the commandto the CM section 170 a.

[0242] When the CM section 170 a is ready to process and receives an ACKsignal, it transmits an ACK to the CM access circuit 113. The reasonswhy REQ-ACK protocol for the CM unit 170 is necessary will be describedherein.

[0243] If the CM unit 170 has a buffer having a size large enough toreceive data, the REQ-ACK protocol is unneeded. More particularly, thedata may be saved in the buffer and thereafter may be written from thebuffer to the CM at the time the controller of the CM unit 170 is readyto process.

[0244] But, generally, the length of data to be transferred is large incase of cache access (in the present embodiment, 2 KB is assumed) and itis wasteful from the standpoint of costs to provide buffers for theindividual cache access paths 130.

[0245] Thus, by returning the ACK to the CM selector 150 at the timethat the CM unit 170 is ready to process and by transferring transferreddata directly to the CM unit, the aforementioned buffer can be dispensedwith.

[0246] In case of SM unit access, the size of one transfer operation issmall amounting up to about 1 word and therefore the buffers areprovided for the individual SM access paths, without doing matter.

[0247] Therefore, the REQ-ACK protocol from the SM selector 140 to theSM unit 160 is unneeded and the command, address and data are stored inthe register 310.

[0248] Now, when the CM access circuit 112 receives the ACK, ittransfers the address and data and waits for an end report.

[0249] The CM selector circuit transfers the address and command to theCM section 170 a which is an object to be accessed. When the CM section170 a completes write of the data, the CM selector circuit receives anend report and transfers it to the CM access circuit 112, therebycompleting the process.

[0250] Thereafter, the CM access circuit 112 executes the process ofwrite to the CM section 170 b. The sequence of this write process issimilar to that of write operation to the CM section 170 a and will notbe described herein.

[0251] Through the above procedure, dual write of one packet to the CMsections 170 a and 170 b is completed. Thus, this process is repeatedfor all packets.

[0252] In the present embodiment as above, the command, address and dataare transferred in correspondence to the CM sections 170 a and 170 b andtherefore, the utilization efficiency of the MP

CM access paths 130 and 135 and the CM selector 150 is bad.

[0253] Accordingly, another embodiment is directed to solve this problemas will be described below.

[0254] Referring to FIG. 13, there is illustrated a sequence of dualwrite to the CM unit 170.

[0255] The CM access circuit transfers to the CM selector 150 a commandtogether with a REQ signal.

[0256] The command is a write access command in which a dual accessflag, an access flag to the CM section 170 a and an access flag to theCM section 170 b are on.

[0257] When receiving the command, the CM selector 150 transfers the REQsignal and the command to both the CM sections 170 a and 170 b.

[0258] When both the CM sections 170 a and 170 b are ready to processand they return ACK signals, the CM selector circuit 150 transmits anACK signal to the CM access circuit 112.

[0259] Thereafter, the CM access circuit 112 transfers an address of theCM section 170 a, an address of the CM section 170 b and write data tothe CM selector 150 and then, the CM selector 150 transfers the addressof CM section 170 a to the CM section 170 a and the address of CMsection 170 b to the CM section 170 b. The write data is transferred toboth the CM sections 170 a and 170 b.

[0260] As in the immediately previous embodiment, the CM unit 170 storesthe write data at the designated address and then makes an end report tothe CM access circuit 112 through the CM selector 150.

[0261] According to the present embodiment, one transfer operation ofwrite data suffices and occupation time of the MP-CM selector accesspaths 130 can be reduced correspondingly.

[0262] Further, the CM sections 170 a and 170 b are processed inparallel and therefore, the response can be shortened.

[0263] In still another embodiment of the invention, a method of copyingdata between CM sections will be described.

[0264] Conceivably, a copy originator and a copy destination in copyingbetween the CM sections are switched in four ways, that is, from CMsection 170 a to CM section 170 a, from CM section 170 b to CM section170 b, from CM section 170 a to CM section 170 b, and from CM section170 b to CM section 170 a.

[0265] Firstly, a method applicable to the above four ways will bedescribed in which data is read out of a copy originator CM section tothe buffer 115 by using the buffer 115 of the MP section and thereafterthe data is copied from the buffer 115 to a copy destination CM section.

[0266] Referring to FIG. 14, the sequence of the inter-cache copyingmethod through the medium of the buffer 115 will be summed up.

[0267] In case the buffer 115 intervenes, copying which exceeds inamount the capacity of the buffer 115 cannot be effected through oneoperation and a plurality of copying operations need to be carried out.These operations are controlled by the MP 111.

[0268] The MP 111 first prepares a DMA list of a read request for thecopy originator CM section (in FIG. 14, CM section 170 a) and a DMA listof a write request for the copy destination CM section (in FIG. 14, CMsection 170 b) and starts the CM access circuit 112.

[0269] Here, the upper limit of the size of transfer in the DMA listequals the buffer size or capacity.

[0270] Through the method set forth so far, the CM access circuit firstreads data from the copy originator CM section 170 a and delivers it tothe buffer 115.

[0271] When this operation is completed, the CM access circuitsubsequently writes the data from the buffer 115 to the copy destinationCM section 170 b to complete the process and informs the MP 111 of thecopy completion.

[0272] The MP 111 does not intervene during a time interval ranging fromcommanding the copy start to receiving the end report.

[0273] In case data to be copied still remains because of the limitedbuffer size, the MP successively prepares a DMA list and continues thecopy process.

[0274] Next, still another embodiment directed to an inter-cache copymethod without resort to the intervening buffer 115 will be described.

[0275] In this method, data read out of a copy originator is turned backat the CM selector 150 so as to be transferred to a copy destination.

[0276] Since the data flows to pass through the CM selector 150 (withoutbeing stored in the buffer), CM sections representing the copyoriginator and copy destination must differ from each other. In otherwords, this method is applicable only to either copying from CM section170 a to CM section 170 b or copying from CM section 170 b to CM section170 a.

[0277] Referring to FIG. 15, the sequence of the inter-cache copyingmethod in which data is turned back at the selector will be summed up.

[0278] The MP 111 prepares a DMA list for execution of the inter-cachecopy and thereafter, starts the CM selector 150 by asserting a REQsignal.

[0279] Here, an inter-cache copy command, a copy originator address anda copy destination address are included in the list.

[0280] When started, the CM selector 150 issues requests for copy toboth a copy originator (In FIG. 15, CM section 170 a) and a copydestination (in FIG. 15, CM section 170 b).

[0281] Both the CM sections 170 a and 170 b are ready to process andthey return ACK's to the CM selector which in turn returns an ACK to theCM access circuit 113.

[0282] Responsive to the ACK, the CM access circuit 113 transmits acommand, an address of CM section 170 a and an address of CM section 170b to the CM selector.

[0283] The CM selector 150 transfers the command to both the CM sections170 a and 170 b, the address of CM section 170 a to the CM section 170 aand the address of CM section 170 b to the CM section 170 b.

[0284] When data is read out of the copy originator CM section 170 a,the data is transferred to the copy destination CM section 170 b.

[0285] Like the write process, the CM section 170 b is ready to receivethe data and stores the received data at the designated address.

[0286] The above read process from the CM section 170 a and the writeprocess to the CM section 170 b are repeated until copying of all datais completed.

[0287] Advantages of the two inter-cache copying methods will be summedup as below.

[0288] In the copying method in which data is turned back at the CMselector 150, read from the copy originator and write to the copydestination can be carried out in parallel.

[0289] Since the data read out of the copy originator is not saved inthe buffer, copying of data of any size can be completed by oneoperation start.

[0290] Accordingly, as compared to the copying method in which thebuffer 115 intervenes, time consumed by copying can be shortened.

[0291] On the other hand, because of transfer of copy data directly tothe copy destination without saving data to the buffer, there arisessuch a disadvantage that copying between the same sections, that is,copying from CM section 170 a to CM section 170 a and copying from CMsection 170 b to CM section 170 b cannot be ensured.

[0292] Accordingly, it is preferable that copying between the samesections be carried out in accordance with the copying method in whichthe buffer 115 intervenes and copying between the different sections becarried out in accordance with the copying method in which data isturned back at the CM selector 150.

[0293] In the foregoing embodiments, the storage control apparatus 195has been described as being a typical example constructed as shown inFIG. 1 but the present invention may be applied to the storage controlapparatus constructed as below to attain similar effects to thosedescribed hereinbefore.

[0294] Referring to FIG. 16, there is illustrated in block form anexample of the basic construction of the storage control apparatusaccording to the invention. The storage control apparatus of FIG. 16comprises a selector group 190A including two MP units 110A and 110Bwhich are coupled to a CPU 225 and a storage unit 226, respectively, oneSM selector 140 and one CM selector 150, one SM unit 160 and one CM unit170. Each of the MP units 110A and 110B is coupled to the SM selector140 and CM selector 150 through access paths, the SM selector 140 iscoupled to the SM unit 160 through one path and the CM selector 150 iscoupled to the CM unit 170 through one path. Accordingly, the number (1)of CM access path for coupling the CM selector 150 to the CM unit 170can be smaller than the number (2) of CM access paths for coupling eachof the MP units 110A and 110B to the CM selector 150. Similarly, thenumber (1) of SM access path for coupling the SM selector 140 to the SMunit 160 can be smaller than the number (2) of CM access paths forcoupling each of the MP units 110A and 110B to the SM selector 140. Itwill be appreciated that more than two selector groups may be provided(in FIG. 16, another selector group 190B is illustrated).

[0295] Referring to FIG. 17, there is illustrated in block form amodification of the FIG. 16 storage control apparatus. In the storagecontrol apparatus of FIG. 17, each of the SM unit 160 and CM unit 170 ismade to have a dual structure in order to increase the storage capacityand improve the reliability. More particularly, the storage controlapparatus comprises a selector group 190A including two MP units 110Aand 110B which are coupled to a CPU 225 and a storage unit 226, one SMselector 140 and one CM selector 150, two SM sections 160 a and 160 band two CM units 170 a and 170 b. Each of the MP units 110A and 110B iscoupled to the SM selector 140 and CM selector 150 through access paths,the SM selector 140 is coupled to each of the SM sections 160 a and 160b through one path and the CM selector 150 is coupled to each of the CMsections 170 a and 170 b through one path. It will be appreciated thatmore than two selector groups may be provided (in FIG. 17, anotherselector group 190B is illustrated).

[0296] Referring to FIG. 18, there is illustrated in block form anotherexample of the basic construction of the storage control apparatusaccording to the invention. In the storage control apparatus of FIG. 18,one selector functionally serves both as a SM selector and a CM selectorand in addition, part of a CM unit is used as a SM unit. Moreparticularly, in FIG. 18, the storage control apparatus comprises aselector group 190A including two MP units 110A and 110B which arecoupled to a CPU 225 and a storage unit 226, respectively, and oneselector 145, and one CM unit 170 part of which is usable as a SM unit.In this case, a SM area and a CM area in the memory 170 may bedistributed in accordance with addresses and the SM area or the CM areamay be accessed selectively in accordance with an address received by anaccess circuit in the memory 170. Alternatively, access to the SM areamay be discriminated from that to the CM area by changing protocol, theSM area may be discriminated from the CM area by adding, to an accessrequest, information concerning access to the SM area and CM area, orthe SM area may be discriminated from the CM area by adding, to acommand, information concerning access to the SM area and CM area. Inthis construction, each of the MP units 110A and 110B is coupled to theselector 145 through an access path and the selector 145 is coupled tothe CM unit 170 through one path. Accordingly, the number (1) of CMaccess path for coupling the selector 145 to the CM unit 170 can besmaller than the number (2) of CM access paths (2) for coupling the MPunits 110A and 110B to the selector 145. It will be appreciated thatmore than two selector groups may be provided (in FIG. 18, anotherselector group 190B is illustrated).

[0297] Referring now to FIG. 19, a modification of the FIG. 18 storagecontrol apparatus is illustrated in block form. In this modification,there are provided more than three MP units and two selectors in oneselector group. Further, the CM unit has a dual structure. Moreparticularly, each of the MP units 110a1, 110a2, 110b1 and 110b2 iscoupled to selectors 145A and 145B through access paths, and each of theselectors 145A and 145B is coupled to CM units 170 a and 170 b throughpaths. Accordingly, the number (2) of access paths for coupling theselector 145A to the CM units 170 a and 170 b can be smaller than thenumber (4) of access paths for coupling the MP units 110a1, 110a2, 110b1and 110b2 to the selector 145A. Similarly, the number (2) of accesspaths for coupling the selector 145B to the CM units 170 a and 170 b canbe smaller than the number (4) of access paths for coupling the MP units110a1, 110a2, 110b1 and 110b2 to the selector 145B. It will beappreciated that more than two selector groups may be provided (in FIG.19, another selector group 190B is illustrated).

[0298]FIG. 20 is a block diagram showing a modification of the storagecontrol apparatus shown in FIG. 16. The modification of FIG. 20 differsfrom the storage control apparatus shown in FIG. 16 only in a point thatlike the arrangement of FIG. 18 the SM selector 140 and the CM selector150 of FIG. 16 are formed as a single selector 145 so that the selector145 serves both as the SM selector 140 and the CM selector 150 of FIG.16.

[0299]FIG. 21 is a block diagram showing a modification of the storagecontrol apparatus shown in FIG. 20. The modification of FIG. 21 differsfrom the storage control apparatus shown in FIG. 20 only in a point thatthe SM unit 160 of FIG. 20 is arranged to have a dual structure of SMsections 160 a and 160 b and also the CM unit 170 of FIG. 20 is arrangedto have a dual structure of CM sections 170 a and 170 b.

[0300] In the foregoing embodiments, the storage control apparatus hasbeen described as being exemplarily coupled to the single CPU and thesingle storage unit but the storage control apparatus may be coupled toa plurality of CPU's and a plurality of storage units.

[0301] As described above, according to the present invention, byinterposing the selector between a plurality of processors and aplurality of memory units and selecting and executing a request foraccess to a memory unit by means of the selector, the number of wiringlines per package can be reduced and the shortage of the number of pinsand of package connectors in a LSI can be eliminated.

[0302] In addition, according to the invention, by defining one sectionof a SM unit having a dual structure as master and the other as slaveand providing a mechanism in which the SM sections are interconnectedtogether and the slave executes a dual access request only when arequest for processing is received from the master, the dual state canbe maintained between the SM sections.

1. (Original) A storage control apparatus coupled to a centralprocessing unit and a storage unit to control input/output of databetween said central processing unit and said storage unit, comprising:at least two processors coupled to said central processing unit and saidstorage unit; a cashe memory unit for temporarily storing data of saidstorage unit; a shared memory unit for storing information concerningcontrol of said cashe memory unit and said storage unit; and a selectorcoupled to each of said at least two processors, said cashe memory unitand said shared memory unit through access paths to selectively applyaccess requests from said at least two processors to said cashe memoryunit and said shared memory unit. Claims 2-19 (Canceled)